The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device which can prevent the excessive loss of an isolation structure and the occurrence of a defect when forming a pin transistor.
As the design rule of a semiconductor memory device abruptly decreases, the length and the width of the channel of a transistor decrease, and the doping level of a junction region increases, so that a junction leakage current increases due to the increase of an electric field. According to this, in the conventional transistor having a two-dimensional planar channel structure, it is difficult to obtain a threshold voltage demanded in a high integration semiconductor device, and limitations exist in improving a refresh characteristic. In consideration of this fact, research have actively been made to develop a transistor having a three-dimensional channel structure in which a channel length can be increased. As a result of the research, recently, a pin transistor having a three-dimensional channel structure has been disclosed in the field of a logic device.
In the pin transistor, an active region is relatively projected by etching a field region, and gates are formed to border the projected active region. As the side surfaces, as well as, the upper surface of the projected active region form a channel area, the resultant pin transistor results in having an increased channel length when compared to a transistor having a planar structure. Hence, in the pin transistor, an excellent current driving characteristic can be attained through the momentary increase of a current amount. Also, since an on/off characteristic of the pin transistor is excellent, a semiconductor device having a high operation speed can be realized. In addition, because the pin transistor has low back bias dependency, a desired device characteristic can be attained.
Hereafter, a conventional pin transistor will be schematically explained.
FIG. 1 is a plan view of a semiconductor device, and FIGS. 2A through 2C are cross-sectional views taken along the lines A-A′ and B-B′ of FIG. 1, which illustrates some of the processes of more conventional methods for manufacturing a semiconductor device. In FIG. 1, the reference numeral A/R designates an active region, F/R a field region, and G a gate.
Referring to FIG. 2A, a trench T is defined by etching the field region F/R of a semiconductor substrate 200 having an active region A/R and a field region F/R. By forming an insulation layer in the trench T, an isolation structure 216 is formed. The isolation structure 216 is formed as a stacked layer of an SOG (spin-on glass) oxide layer (hereinafter, referred to as an “SOG layer”) 212 and an HDP-CVD (high density plasma-chemical vapor deposition) oxide layer (hereinafter, referred to as “HDP layer”) 214. The reason to form the isolation structure 216 in this way is to improve a trench filling characteristic for filling a trench which has a fine size due to the high integration of a semiconductor device.
Referring to FIG. 2B, the HDP layer 214 and a partial thickness of the SOG layer 212 of the isolation structure 216 are etched so that the side surfaces of the active region A/R are exposed. As a result of the etching, when viewed in a channel width direction, that is, in the direction of the line B-B′, the HDP layer 214 is entirely removed, and the SOG layer 212 is exposed.
Referring to FIG. 2C, a cleaning process is conducted for the semiconductor substrate 200 having the etched isolation structure 216, using for example either a diluted HF solution or a diluted NH4F solution. At this time, due to the fact that the SOG layer 212 has a greater etch rate than the HDP layer 214 in the diluted HF solution or the diluted NH4H solution, as a result of the cleaning process, a bowing phenomenon occurs in which the SOG layer 212 is etched more than the HDP layer 214.
After a gate insulation layer 222, a polysilicon layer 224, a metallic layer 226 and a hard mask 228 are sequentially formed on the cleaned semiconductor substrate 200, by etching these layers 228, 226, 224 and 222, a gate 230 is formed.
Thereafter, while not shown in the drawings, by forming source and drain areas in the active region A/R of the semiconductor substrate 200 on both sides of the gate 230, a pin transistor is formed.
However, in the conventional method of manufacturing a semiconductor device for the formation of a pin transistor, problems are caused in that a short circuit occurs between adjoining gates, and the operation speed of a semiconductor device decreases due to parasitic capacitance. That is to say, in the conventional art, a bowing phenomenon occurs on the SOG layer in the cleaning process, and when gate processes are conducted with the bowing phenomenon occurred, as shown in FIG. 3, the polysilicon layer 224 remains in the bowing areas of the SOG layer 212. Thus, a short circuit occurs between adjoining gates due to the remaining of the polysilicon layer 224, parasitic capacitance increases, and the operation speed of the semiconductor device decreases. In particular, as the integration degree of a semiconductor device increases, the height, that is, the deposition thickness of the SOG layer 212 must be increased to fill a trench having a fine size, and the etch depth of the isolation structure 216 must be increased. Therefore, in the manufacture of the pin transistor, the exposure of the SOG layer 212 is inevitable, and it is expected that the problems caused therefrom will become more serious.